FIG. 1 is a plan view of an example of a conventional semiconductor device, and FIG. 2 is a cross-sectional view along line 2--2 in FIG. 1. As shown in FIGS. 1 and 2, on a chip substrate 1 of an insulating ceramic having good thermal conductivity, such as beryllia (BeO), metallized electrodes 21, 22, and 23 are disposed in a predetermined pattern. As the metallized electrodes, three-layer electrodes having a structure such as W/Ni/Ag, W/Ni/Au, MoMn/Ni/Ag, or MoMn/Ni/Au may be used.
A base lead 3 and a collector lead 4 are brazed to the top surfaces of the metallized electrodes 21 and 23, respectively. The substrate with the metallized electrodes and the base and collector leads 3 and 4 brazed to the respective metallized electrodes is referred to as a chip carrier. A high-frequency, high-power transistor 5 is mounted on the chip carrier with its collector C contacting the metallized electrode 23. An MOS capacitor 6 is mounted on the metallized electrode 22. A metallic bridge 7 is disposed above and across the metallized electrode 23 and is connected to the metallized electrode 22.
The emitter E of the transistor 5 is electrically connected to the metallized electrode 23 and to the metallic bridge 7 by wires 8, and the base B is electrically connected to the MOS capacitor 6 by wires 9. The MOS capacitor 6 is electrically connected to the metallized electrodes 21 by wires 10. The metallic bridge 7 is provided for reducing the parasitic inductance associated with the emitter electrode wiring of the transistor 5. The metallized electrode 22 is connected to a metallized grounding electrode 12 disposed on the opposite surface of the substrate 1 by a metallization 11 on the sides of the substrate 1. The MOS capacitor 6 is connected in the circuit between the base of the transistor 5 and ground in order to cancel the parasitic inductance that could be introduced into the circuit by the wires 8, 9, and 10. As shown in FIG. 3, the MOS capacitor 6 may be formed by disposing an n.sup.+ -type semiconductor layer 17 on the metallized electrode 22, an SiO.sub.2 layer 18 on the layer 17, and an Au layer 19 on the layer 18. The wires 9 and 10 are bonded to the Au layer 19.
The semiconductor device shown in FIGS. 1 and 2 comprises a chip 16 mounted on arms 14 and 15 of a frame 13, as shown in FIG. 4. The frame 13 is an Ni alloy, such as Kovar (29%Ni--17%Co--Fe) and 42 alloy (42%Ni--Fe). The arms 14 and 15 are cut to a desired length to provide the base lead 3 and the collector lead 4.
Because of the metallic bridge 7, which is provided for reducing the parasitic inductance of the wire 8 connected to the transistor, in particular, its emitter E, a high degree of integration on the chip carrier cannot be achieved. The side metallization 11, which is used for connection to the bottom metallized ground electrode 12, has a parasitic inductance that is not negligible so that an adequate high frequency characteristic cannot be realized. Therefore, an object of the present invention is to provide a small-sized semiconductor device including a transistor having a reduced parasitic inductance. The reduction of the size improves the degree of integration.